Digital System Test And Testable Design: Using ... -

It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms.

Scan architectures, RT-level scan design, and Boundary Scan (JTAG). Digital System Test and Testable Design: Using ...

Memory fault models, MBIST (Memory BIST) methods, and functional procedures. It utilizes Verilog models and testbenches to implement

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies. RT-level scan design

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .

Random and deterministic test generation methods, plus sequential circuit test generation.